这些RFIC问题，知多少？

无意中发现这些RFIC问题，并试图回答，发现还有不少知识盲点，有的虽然知道但也需翻书温故一下，不少问题展开细说，还可以说的很深入。这些问题据说是来自国际大厂如Apple,Qualcomm,MTK等RFIC的面试题。虽说是RFIC的提问，也包含了很多模拟IC问题，毕竟，模拟知识是RF设计的基础。在这里分享给大家，检验下自己的基础，共同进步

These are the questions that were asked in real interviews at companies like Apple, Qualcomm, MediaTek, Intel, Samsung, Skyworks, Keysight, pSemi, Qorvo, Anokiwave etc. for positions of senior to staff engineer.

1. How will you design a PA with 30 dBm output power? What load impedance for PA will you choose, at what point will you start thinking of power combining?

2. Breakdown mechanisms in MOS. How it happens? What is gate breakdown, what is drain source breakdown etc.? Go into physics of breakdown.

3. Have you designed any ESD protection circuit?

4. What is the impedance looking into gate of transistor with degeneration inductor?

5. Say you have matched LNA by doing source degeneration and a series inductor at input. What is the overall transconductance of the circuit?

6. How can you introduce real part in input impedance of CS amplifier?

7. How does device size affect noise in LNA design?

8. Can you derive the noise figure of common source amplifier?

9. How do you optimize transistor (in terms of bias, device size and layout) for ft, fmax and NF

10. Do you know how to design bandgap, PTAT etc?

11. There are two current mirror transistor, one mirroring current from other. How do you increase the matching between the transistors?

12. How can you match Vth of transistors?

13. Vth increases with channel length or decreases? why?

14. Increasing bias current of cmos increases the voltage gain or decreases it?

15. How would you design two stage amplifier? Do you know how to compensate it?

16. Why Miller compensation does pole splitting? You also add some resistor in Miller compensation, why?

17. What is input impedance of CS amplifier with and without Cgd cap?

18. Derive output impedance expression of CS amplifier including Cgd.

19. How to increase gain of amplifier? How do you increase output impedance? Add current source load, stack devices, super transistor, how else?

20. What is the IIP3 of two cascaded blocks? Under what conditions this cascade IIP3 formula is not valid?

21. How is IM3 affected when you increase one tone amplitude and other remains fixed?

22. What is the relation between IIP3 and HD3?

23. What is the noise figure of two cascaded amplifiers?

24. Say you are given two amplifiers with some NF. You cannot change the amplifier design. Is there anything you can do to reduce the system noise?

25. What linearity metrics do you use for PAs? (P1,IIP3,ACLR,EVM,AM-AM, AM-PM)

26. How does AM-AM or AM-PM effect EVM?

27. Do you know what is memory effect?

28. Draw Pout vs Efficiency curve of class A, B and AB amplifier

29. If you are in class AB, how can you increase efficiency of the PA? assume passives are ideal.

30. How do you bias PA? How do you take care of thermal runaway?

31. What breakdown voltage in lower in CMOS and why? gate to drain or drain to source?

32. For which impedance do you match your PA? Your signal has PAPR, your output impedance is dynamically varying. Which impedance would you choose?

33. What is active load pull? Why do you use it?

34. Cascode LNA. How do you choose device size of input transistor? How do you choose Lg and Ls inductors? How do you choose cascode transistor size? How does cascode affect NF?

35. Draw time domain waveform of output of RC and RL low pass and high pass filters if the input is square wave.

36. What is current crowding in inductors? what are step symmetric inductors? pros and cons between signle ended and differential inductors?

37. If you have CS amplifier, and gate is terminated with very high impedance, assume there is Cgd capacitance. What is the output impedance?

38. How do you match 200 to 50 ohms? what is S21? Suppose the matching inductor has 1ohm series resistance. What will be the S21 now? (popular question)

39. What is the resonance frequency, Q and BW of parallel RLC tank?

40. Series resistor and inductor. If you adjust there values in such a way that Q remains same. How would it move on Smith chart for different values of R?

41. Say a typical oscillator circuit with LC load. What is the output impedance when it oscillates? What is the output impedance when it is in transient phase where oscillations are trying to build-up?

42. Say parallel LC tank. What is the current in tank during resonance vs source current?

43. What happens if I,Q are mismatched in RX? what about in TX?

44. How do you layout a transistor? what techniques do you use to reduce parasitis? How to choose number of fingers?

45. Pole zero analysis of typical OTA

46. Say single stage differential opamp. If load transistors have mismatch, dc offset is produced. How would you take care it? Like how would you size the transistors, big or small?

47. What is the significance of ft (transition frequency) and fmax (frequency at which unilateral gain becomes one) of transistor

48. This is a current mirror circuit. Say noise is added at this point. What will be its transfer function to output?

49. Input impedance of CG? What is impact of positive feedback from ro on input impedance?

50. How does AM-AM and AM-PM affects IM3s?

51. What is single side band modulation?

52. Movement of constellation points (in EVM measurements) with AM-AM, AM-PM, noise, memory effect etc

53. If antenna impedance is varying, how do you take care of it in PA design?

54. An ideal amplifier with gain -1, input output connected with resistor R, what is the Zin?

55. How does the spectrum of square wave look like? What if you change the duty cycle to 25%?