Minimizing Cost and Time to Market for O-RAN Hardware

This blog post takes a look at the technologies and support that semiconductor manufacturers can provide for rapid and cost-effective development of Open Radio Access Network hardware.

Open RAN Explained: Innovation and Flexibility

The drive to implement Open Radio Access Network (O-RAN) 5G infrastructures was recently brought into sharp focus with the announcement that the U.S. CHIPS Act of 2022 would allocate $1.5 billion of funding to the development of O-RAN systems.

An initiative of the Open-RAN Alliance, O-RANs allow mobile network operators (MNOs) to move away from closed, proprietary systems to open infrastructures built around multi-vendor ecosystems. This realizes cost and performance benefits while providing more flexible network possibilities (including the ability to serve smaller, tightly defined 5G networks). O-RAN should also enable faster innovation thanks to the ability to choose interoperable technologies from a variety of vendors rather than being tied in to closed, proprietary systems.

To be competitive in this brave new open and interoperable world, existing and emerging technology vendors must develop advanced solutions for O-RAN hardware—including the Radio Unit (RU), Distributed Unit (DU), Centralized Unit (CU) and RAN Intelligent Controller (RIC) functional blocks shown in Figure 1—while maintaining the lowest cost and shortest development time.

Figure 1: Key functional blocks of an O-RAN system

Solutions for O-RAN

One way to address budgetary and time-to-market challenges is to specify application-specific standard parts (ASSPs), or what the defense sector might refer to as commercial-off-the-shelf (COTS) products. The variety and performance of standard semiconductors available to today’s O-RAN system architects, for instance, continues to grow, meaning there are fewer reasons to choose more expensive specialized chips or spend time and resources creating custom Integrated Circuits (ICs).

Take, for example, timing and network synchronization.

Keeping RUs and DUs in sync is important for effective O-RAN operation and ensuring that MNOs are fully compliant with the terms of their frequency licenses. Flexibility in adjusting inbound-to-outbound transmissions based on network demand means that Time division multiplexing (TDD) based on the IEEE 1588 Precision Timing Protocol (PTP) is used to ensure the most efficient use of the channel. Among the ASSP components now available to support IEEE 1588 PTP are high-accuracy PLLs and buffers, ‘grandmaster’ clocks, primary reference time clocks (pRTCs) and precision oscillators.

It’s a similar story when implementing the seamless network connectivity at the heart of O-RAN systems.

Here, standard components include high-performance, small-footprint, low-power Ethernet transceiver (PHY) ICs designed for speeds ranging from 10 Mbps to 1000 Gbps and capable of handling up to 64 ports, single-chip Ethernet switches and ICs for optical networking. These devices support the higher data rates that O-RAN networks demand and, in the case of the Microchip portfolio, provide the support for IEEE 1588v2, SyncE and time-sensitive networking (TSN) functionality that is fundamental to O-RAN interoperability.

For O-RAN RUs, the latest standard silicon and gallium arsenide varactor diodes offer large tuning ratios and high Q values and are ideally suited to beam forming applications, while GaN-based millimeter wave (mmWave) power amplifiers can improve so-called SWaP (Size, Weight and Power) figures of merit to improve performance while delivering smaller, lighter and more efficient units.

On the subject of efficiency, the need to reduce energy consumption is a common theme across all elements of an O-RAN implementation as operators seek to keep operating costs down and achieve environmental targets. Off-the-shelf semiconductors that help address this requirement include digital and analog power management ICs (PMICs) and Power over Ethernet (PoE) chips that enable efficient deployment of PoE technology to Ethernet-based devices. Energy-efficient Field Programmable Gate Array (FPGA) architectures will also help as FPGAs become more prominent and account for larger portions of power budgets.

Figure 2: ASSP ICs for end-to-end O-RAN solutions

Figure 2 illustrates how Microchip technologies such as those described above—FPGAs and ICs that address the cybersecurity challenges facing O-RAN operators—come together to provide a complete, end-to-end O-RAN system solution built on off-the-shelf ASSPs.

Beyond the Chips

The ability to use standard products is not limited to individual semiconductors but can also be considered in the context of choosing commercially available standard hardware that employs those semiconductors. Such hardware further minimizes the design overhead on O-RAN system architects and integrators by providing completed systems that can be quickly integrated into O-RAN architectures.

Among the solutions offered are platforms that allow designers to quickly implement Ethernet connectivity, Precise Time Scale Systems (PTSS) that provide secure, robust and resilient sources for UTC-class time and flexible gateway clock hardware platforms that provide secure and accurate IEEE 1588-compliant time and synchronization (figure 3).

Figure 3: Microchip’s 1588 v2 PTP grandmasterwith PTP, NTP and SyncE capabilities is a good example of a hardware platform for O-RAN

There are other factors that will help designers drive down the cost and time spent on taking an O-RAN application from design to manufacture. Among these are the availability of tools, reference designs and software that support the semiconductor hardware.

To complement its IEEE 1588 and SyncE network synchronization products, for instance, Microchip provides its ClockWorks® configurator that allows designers to program devices with any combination of frequency, temperature, ppm and package size to identify the optimum solution for a given application.

For single-chip network synchronization products, we offer evaluation boards and software such as time synchronization algorithms, clock generation APIs and a powerful IEEE 1588 protocol engine that further simplify design and implementation. Software for Microchip FPGAs and processors that brings artificial intelligence (AI) capabilities to the high-performance acceleration cards that provide O-RAN virtualization is also available.

Finally, when selecting a semiconductor supplier, it is worth checking the availability of engineering support, membership of relevant trade bodies and alliances—Microchip, for example, is an active member of the OIF (Optical Internetworking Forum), which promotes the development and deployment of interoperable networking solutions for optical networking products—and long-term component availability, including the handling of end-of-life (EoL) situations.

Summary

Increased availability of ever-more-advanced and higher performance standard semiconductors and hardware platforms will help O-RAN system architects and hardware designers move away from proprietary, specialized technologies, simplifying development, reducing costs and minimizing time-to-market. Deciding to use ASSPs and standard platforms, however, is by no means the whole story.

Factors such as the availability of end-to-end solutions, reference designs, software and algorithms—as well as access to engineering experience—all have a role to play in supporting efficient and effective O-RAN prototyping and development with minimum design spins.

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