| CMSIS-CORE Version 3.20 CMSIS-CORE support for Cortex-M processor-based devices

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ITM_Type Struct Reference

Structure type to access the Instrumentation Trace Macrocell Register (ITM).

## Data Fields
union {
__O uint8_t u8
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__O uint16_t u16
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__O uint32_t u32
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
} | PORT [32]
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. More...
uint32_t | RESERVED0 [864]
| Reserved. More...
__IO uint32_t | TER
| Offset: 0xE00 (R/W) ITM Trace Enable Register. More...
uint32_t | RESERVED1 [15]
| Reserved. More...
__IO uint32_t | TPR
| Offset: 0xE40 (R/W) ITM Trace Privilege Register. More...
uint32_t | RESERVED2 [15]
| Reserved. More...
__IO uint32_t | TCR
| Offset: 0xE80 (R/W) ITM Trace Control Register. More...

## Field Documentation

__O { ... } ITM_Type::PORT[32]

uint32_t ITM_Type::RESERVED0[864]

uint32_t ITM_Type::RESERVED1[15]

uint32_t ITM_Type::RESERVED2[15]

__IO uint32_t ITM_Type::TCR

__IO uint32_t ITM_Type::TER

__IO uint32_t ITM_Type::TPR

__O uint16_t ITM_Type::u16

__O uint32_t ITM_Type::u32

__O uint8_t ITM_Type::u8